Design and Evaluation of a Network Processor Accelerator for Layer Seven Applications

We present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Many Network Processors employ hardware accelerators for implementing key domain-specific tasks. New applications require new tasks, such as pattern matching, to be performed on network packets in real-time. Using our proposed accelerator, we have implemented several such tasks and measured their performance. The accelerator achieves up to 25-fold improvement on the performance of pattern matching, and 12-fold improvement for tree lookup when compared to optimized software solutions. We present delay, area and power requirements of the accelerator for an ASIC design. We also present a reconfigurable design of the accelerator and present a comparison between these implementations. Since the accelerator can be used for different tasks, the hardware requirements are small compared to an accelerator group that implements the same set of tasks. We also present accurate analytic models to estimate the execution time of these networking tasks.